Resource Management Design in 3D-Stacked Multicore Systems for Improving Energy Efficiency

Technology scaling and increasing power densities have led to a transition from single-core to multi-core processors, and the trend is now moving towards many-core architectures. Hundreds of millions of transistors can now be integrated on a single chip, however, they cannot be fully exploited due to interconnect/memory latency, power consumption, and yield related challenges. 3D integration is an emerging technology aiming to overcome the limitations faced by traditional (2D) design. 3D stacking enables heterogeneous integration of different technologies, increases transistor density per chip footprint, and improves system performance. In 3D systems, multiple layers are stacked on top of each other and interconnected by through-silicon-vias (TSVs). In this way, it is possible to improve yield (owing to the smaller chip area) and also tackle the latency, bandwidth, and power challenges of interconnects. In chip multiprocessors (CMPs), whose performance is typically limited by the memory access bottleneck, increased communication and memory access bandwidths are distinguishing advantages of 3D stacking. Nevertheless, the benefits offered by 3D integration may be strongly limited without an efficient management of the available resources.